z/OS System Anatomy Part 1 - zArchitecture


This course and the associated Part 2 course together form the essential core of the z/OS education curriculum for z/OS Systems Programmers. By attending both components attendees will gain an in-depth insight into the fundamental structure of MVS (now z/OS), enabling further study in areas such as debugging, performance, installation and customisation of the operating system.
This course concentrates on laying the ground rules of z/OS in terms of architecture, storage management, as well as the major control blocks and how to interpret them. The course also introduces the major components found in z Systems environments.

This course is also available for one-company, on-site presentations and for live presentation over the Internet, via the Virtual Classroom Environment service.

Classroom dates (High Wycombe) - click to book!

20 November 2017 9 April 2018

Virtual Classroom Environment dates - click to book!

15 January 2018

What is a 'Virtual Classroom Environment'?

 

What do I need?

  • webcam
  • headphones with microphone
  • sufficient bandwidth, at least 1.5 Mb/s in each direction.

Objectives

On successful completion of this course you will be able to:

  • describe the architectural principles governing CPU, Storage and I/O
  • identify the state of a CPU and describe potential problem scenerios
  • use IPCS and the debugging guides
  • describe the principles of Virtual Storage
  • describe the purpose of AMODE and RMODE
  • describe a page fault and its consequences
  • set up a flexible paging/swapping subsystem
  • explain how dataspaces and hiperspaces work
  • describe how an IPL works
  • isolate problems during an IPL
  • explain the concept of authorised programs.

Who Should Attend

This course is designed for those who wish to gain an in-depth understanding of z/OS systems in order to improve their proficiency in the z/OS environment.

Prerequisites

A good working understanding of the z/OS environment, from a technician's perspective.

Duration

4 days

Fee (per attendee)

£1675 (ex VAT)

Course Code

MSF1

Contents

Architecture

The architectural principles of the CPU; PSW, registers; interrupts system states; PSW swapping; multi-processing; central storage; addressing modes; storage keys; parallel & serial channels; pathing; HCD; LCUs; CCWs; I/O operation; SCSW.

MVS Introduction

The functions of the MVS operating systems; components required to prepare MVS for work; creating address spaces; Job Entry Subsystem; initiators; resource control; interrupt handlers and status saving; dispatching work; I/O requests; Workload Manager; execute the work; exit the work from the system.

Control Blocks, Dumps & IPCS

Using IPCS and the debugging handbooks to locate and interpret major MVS control blocks in a dump; finding main control blocks such as PSA, CVT, ASCB, TCB, UCB; main IPCS menus; IPCS FIND command; IPCS subcommands; IPCS labs.

Virtual Storage Concepts

Loading programs; real storage problems; DAT; segments & pages; page stealing & UIC; page faults; demand paging; dispatching address spaces; swapping & paging.

MVS Storage Management

AMODE & RMODE; common storage; private storage; Virtual Storage Manager; subpools; storage keys; RSM; page faults; segment faults; ASM; page data sets; VIO.

Dataspaces and Hiperspaces

Primary & secondary ASC modes; access registers; using dataspaces; VLF; Hiperspaces.

System Initialisation

Sysgen and IPL processes; the function of the LOAD parameter and the LOADxx member of PARMLIB; concepts of authorised programs; the subsystem interface.


What the students say

I really enjoyed the way Carol presented the course. It made a very complex course seem a little easier.

Senior Systems Programmer

Barclays Bank plc

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